This invention relates to transistor transistor logic (TTL) output circuits, and more particularly to a circuit which compensates for so-called "Miller current," a current pulse that charges the capacitance of the base-collector junction during the turn-off of an output "sink" transistor. This current pulse momentarily restarts the sink transistor and degrades the output circuit signal.
A simplified inverting output circuit 10 is shown in FIG. 1. A high voltage input signal Ii applied to input lead 15 produces an inverted and amplified low voltage output signal Io at output lead 80. Conversely, a low voltage input signal Ii produces a high voltage output signal Io. The drive circuit, not shown, providing input signal Ii is isolated or "buffered" by circuit 10 from effects of a load circuit 90 connected to output lead 80.
Input signal phase splitter stage 20 controls and alternately turns on current sink stage 30 and current source stage 40. A high input signal Ii received at input lead 15 and applied to the base of NPN transistor Q1 causes transistor Q1 to conduct. Current from the emitter of transistor Q1 to the base of NPN transistor Q2 causes transistor Q2 to conduct a high "sink control" Q signal, which activates sink 30 when applied to the base of NPN transistor Q3, causing it to conduct. The collector of transistor Q3 draws, "pulls," or "sinks" current from output lead 80 connected to external capacitance or load 90, through its collector-emitter current path and out its ground lead.
A low input signal Ii applied to input lead 15 and thus to the base of transistor Q1 stops current through transistor Q1 and hence through transistor Q2, allowing the "source control" voltage of node 24 at the bottom of resistor R2 to rise, which turns on NPN transistor Q4 and NPN transistor Q5. The emitter of transistor Q5 "sources" or "pushes" current through inverter output lead 80 to load 90.
Output transistors Q3 and Q5 must be physically larger than other transistors in inverter circuit 10 to provide an output current effective to drive or switch the output load 90 capacitance quickly. The large capacitance of the base of transistor Q3 stores charge during conduction, which must be discharged to turn off transistor Q3 in switching to a high output signal Io. Resistor R6 provides a conductive path to discharge the base of transistor Q3 to ground. Transistor Q3 also has a large collector-base capacitance, known as "Miller capacitance" Cm. FIG. 2 shows an equivalent circuit model of sink transistor Q3, in which Miller capacitance Cm is represented distinct from, and connected in parallel to, the base-collector junction.
In switching output signal Io, phase splitter stage 20 (FIG. 1) turns on current source stage 40 simultaneously with turning off sink stage 30. When both transistors Q3 and Q5 are midway in switching, the forward bias of the base-emitter junction of transistor Q3 is falling below 0.7 volts while transistor Q5 is switching on and raising the voltage of output lead 80. The rapidly increasing reverse bias of the base-collector junction of transistor Q3 causes a transient "Miller current" Im=Cm(dv/dt) from output lead 80, to charge Miller capacitance Cm. Thus, Miller current charging capacitance Cm is proportional to the rate of change of the collector-base voltage (dv/dt) of transistor Q3. Miller current is more of a problem when output signal Io drives a load 90 having a low capacitance, which is charged rapidly and allows a faster voltage rise on the collector of transistor Q3, coupling a larger (albeit briefer) Miller current into the base of transistor Q3. If the base-emitter junction of transistor Q3 is forward biased, then part of current Im will flow across the base-emitter junction of transistor Q3 as current Ib. Current Ib originates from charging the Miller capacitance Cm, rather than from a control signal applied to the base lead as in usual transistor operation. While Miller current Im does offset output current Io by a small amount, this would not be serious except that current Ib momentarily restarts transistor Q3, sinking collector current If=Ib times the beta of transistor Q3. With typical transistor Q3 beta values of 50, this undesired collector current can be rather large. Output node current Ic=Im+If causes a dip, ("spike" or "glitch") in the rising output signal Io, as shown in FIG. 3. This draws current spikes from power supply Vcc, wasting power and causing excessive heating. If the glitches are large enough that signal Io falls below the threshold of load stage 90, the glitches can propagate beyond load 90 into a connected system (not shown).
Miller current Im cannot be prevented, but, by lowering the voltage on the base of transistor Q3, Miller current Im can be split into current Ib and a current Id (FIG. 2) which is diverted out the base lead and flows away from the base. Since Ib=Im-Id, any of current Im that is diverted from current Ib to current Id is not beta multiplied to cause current If spikes in output current Io. If all of current Ib were diverted as current Id, there would be no current If, and Miller current would not be a serious problem. Resistor R6 of FIG. 1 is a passive circuit element which sinks a constant amount of current depending on the value of the resistance and of the voltage across it. Resistance R6 provides the least Miller current protection of the prior art circuits. If the value of the resistance is lowered to shunt more Miller current from the base of transistor Q6 to ground, the overall power consumption of circuit 10 increases.
Other prior art approaches to the problem of Miller current attempt to divert as much of Miller current Im as possible to current Id by means such as the circuits 4a-4d shown in FIG. 4. Prior art circuit 4a uses transistor Q6a connected by resistors R4a to the base of transistor Q3. Circuit 4a is advantageous over resistor R6 mainly in compensating for manufacturing and/or temperature caused variations in the beta of transistor Q3. However, there is no feedback path from a node varying with output signal Io to actively turn on transistor Q6a during a low-to-high output signal transition, so circuit 4a is not very effective in compensating for Miller current.
Other prior art Miller compensating circuits divert charge from the base of transistor Q3 using a transistor as an active element with its base capacitively coupled to, and controlled by, a node in output inverter 10 where the voltage changes in phase with the voltage of output signal Io. For example, in U.S. Pats. No. 4,006,370 to Erler and 4,321,490 to Bechdolt, circuits similar to that shown in FIG. 4b include a relatively large capacitor Cb connected to output lead 80. When transistor Q3 is turning off and transistor Q5 is turning on so that the voltage V of output signal Io is rising, capacitor Cb is charged by a current I4b=Cb(ddv/dt). This is amplified into a transistor Q6b collector current Id=(beta) I4b, to divert current Id from base current Ib and suppress current If (FIG. 2). However, capacitive coupling of capacitor Cb exposes the base of transistor Q3 to adverse effects due to noise from load 90, which can charge capacitor Cb, activate transistor Q6b and accidentally discharge the base of Q3, causing a current spike in output signal Io.
One problem of exposure to "noise" from output load 90 arises during "in-circuit emulation" or testing of a system in which a load circuit 90 is connected to output lead 80. If it is desired to test the system with a low inverter 10 output signal Io, yet for some reason forcing a high signal Io to load 90, a test probe (not shown) is connected to output lead 80 to force a high signal Io. Overriding signal transistor Q3 to rise and causes a current I4b to turn on transistor Q6b, diverting current Ib from, and tending to turn off, transistor Q3 and allowing lead 80, already forced high, to go even higher. However, once the voltage of output lead 80 reaches its upper limit and stops rising, current I4b stops, transistor Q6b stops diverting current Id, transistor Q3 resumes sinking current, and the voltage of output lead 80 starts falling. Because the test probe continues to force output lead 80 high, the output voltage on lead 80 starts oscillating, which, with an appropriate RC time constant in the test probe and/or load circuit 90, can interfere with the desired test.
Other prior art Miller compensating circuits use a capacitor less directly coupled to the output lead. In U.S. Pat. No. 4,132,906 to Allen, a circuit such as circuit 4c connects capacitor Cc to the emitter of transistor Q4 in order to drive Miller current shunt transistor Q6c. This has the disadvantage of not fully buffering Miller compensating circuit 4c from output lead 80, because the base-emitter junction of transistor Q5 acts as a capacitor which is connected in series with capacitor Cc, thereby allowing the Miller current compensating circuit to be undesirably influenced as the voltage of output signal Io rises.
U.S. Pat. No. 4,449,063 to Ohmichi connects one lead of a capacitor Cd to source control node 24 at the bottom of resistor R2, as shown in FIG. 4d. This reduces the adverse effect of capacitive coupling between output lead 80 and the base of shunt transistor Q6d. However, resistively pulled up source control node 24 is excessively loaded by the large capacitance of capacitor Cd, which degrades the switching speed of an output circuit 10 using a compensation circuit such as circuit 4d.
There is therefore a need for a Miller compensating circuit which avoids the prior art drawbacks of capacitively coupling a shunt transistor to the inverter output lead 80, increasing the load on the source stage and exposing the sink stage to noise from the output load.